PIC16C63A/65B/73B/74B
A PWM output (Figure 9-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
9.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
FIGURE 9-4:
PWM OUTPUT
Period
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
Duty Cycle
TMR2 = PR2 (Timer2 RESET)
TMR2 = Duty Cycle
(Timer2 RESET)
TMR2 = PR2
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
9.3.1
PWM PERIOD
When the CCPR1H and 2-bit latch match TMR2, con-
catenated with an internal 2-bit Q clock, or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
Maximum PWM resolution (bits) for a given PWM
frequency:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
FOSC
FPWM
PWM frequency is defined as 1 / [PWM period].
log( )
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
Resolution
bits
=
log(2)
• TMR2 is cleared
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
9.3.3
SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
Note: The Timer2 postscaler (see Section 8.1) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
1. Set the PWM period by writing to the PR2 register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 9-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
5.5
Maximum Resolution (bits)
2000 Microchip Technology Inc.
DS30605C-page 53
MICROCHIP [ MICROCHIP ]
