PIC16C63A/65B/73B/74B
9.2.4
SPECIAL EVENT TRIGGER
9.2
Compare Mode
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
• Driven high
• Driven low
• Remains unchanged
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
Note: The special event trigger from the
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
FIGURE 9-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
9.3
PWM Mode (PWM)
Special event trigger will:
In Pulse Width Modulation mode, the CCPx pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Special Event Trigger
Set Flag bit CCP1IF
(PIR1<2>)
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
CCPR1H CCPR1L
Q
S
R
Output
Logic
Comparator
RC2/CCP1
pin
Match
TRISC<2>
Output Enable
TMR1H TMR1L
Figure 9-3 shows a simplified block diagram of the
CCP module in PWM mode.
CCP1CON<3:0>
Mode Select
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 9.3.3.
9.2.1
CCP PIN CONFIGURATION
FIGURE 9-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
CCP1CON<5:4>
Duty Cycle Registers
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC
I/O data latch.
CCPR1L
CCPR1H (Slave)
Comparator
9.2.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
Q
R
S
RC2/CCP1
(Note 1)
TMR2
9.2.3
SOFTWARE INTERRUPT MODE
TRISC<2>
Comparator
PR2
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set, causing
a CCP interrupt (if enabled).
Clear Timer,
CCP1 pin and
latch D.C.
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock,
or 2 bits of the prescale, to create 10-bit time-base.
DS30605C-page 52
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
