PIC16C62B/72A
2.2.2.3
INTCON REGISTER
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The INTCON Register is a readable and writable regis-
ter, which contains various interrupt enable and flag
bits for the TMR0 register overflow, RB Port change
and External RB0/INT pin interrupts.
REGISTER 2-3:
R/W-0
GIE
bit7
R/W-0
PEIE
INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit0
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit 7:
GIE:
Global Interrupt Enable bit
1
= Enables all un-masked interrupts
0
= Disables all interrupts
PEIE:
Peripheral Interrupt Enable bit
1
= Enables all un-masked peripheral interrupts
0
= Disables all peripheral interrupts
T0IE:
TMR0 Overflow Interrupt Enable bit
1
= Enables the TMR0 interrupt
0
= Disables the TMR0 interrupt
IINTE:
RB0/INT External Interrupt Enable bit
1
= Enables the RB0/INT external interrupt
0
= Disables the RB0/INT external interrupt
RBIE:
RB Port Change Interrupt Enable bit
1
= Enables the RB port change interrupt
0
= Disables the RB port change interrupt
T0IF:
TMR0 Overflow Interrupt Flag bit
1
= TMR0 register has overflowed (software must clear bit)
0
= TMR0 register did not overflow
INTF:
RB0/INT External Interrupt Flag bit
1
= The RB0/INT external interrupt occurred (software must clear bit)
0
= The RB0/INT external interrupt did not occur
RBIF:
RB Port Change Interrupt Flag bit
1
= At least one of the RB7:RB4 input pins have changed state (clear by reading PORTB)
0
= None of the RB7:RB4 input pins have changed state
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
©
1999 Microchip Technology Inc.
Preliminary
DS35008B-page 13
MICROCHIP [ MICROCHIP TECHNOLOGY ]
