PIC16C62B/72A
FIGURE 3-1: BLOCK DIAGRAM OF
3.0
I/O PORTS
RA3:RA0 AND RA5 PINS
Some I/O port pins are multiplexed with an alternate
function for the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Data
Bus
D
Q
VDD
WR
Port
Additional information on I/O ports may be found in the
PICmicro™
(DS33023).
Q
Data Latch
CK
Mid-Range
Reference
Manual,
P
3.1
PORTA and the TRISA Register
I/O pin(1)
N
D
Q
PORTA is a 6-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output, (i.e., put
the contents of the output latch on the selected pin).
WR
TRIS
VSS
Q
CK
Analog
input
TRIS Latch
mode
(72A
only)
TTL
input
buffer
RD TRIS
The PORTA register reads the state of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. There-
fore, a write to a port implies that the port pins are read,
this value is modified, and then written to the port data
latch.
Q
D
EN
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
RD PORT
To A/D Converter (72A only)
Note 1: I/O pins have protection diodes to VDD and
Pin RA5 is multiplexed with the SSP to become the
RA5/SS pin.
VSS.
On the PIC16C72A device, other PORTA pins are mul-
tiplexed with analog inputs and analog VREF input. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register1).
FIGURE 3-2: BLOCK DIAGRAM OF
RA4/T0CKI PIN
Data
Bus
D
Q
Q
WR
PORT
Note: On a Power-on Reset, pins with analog
functions are configured as analog inputs
with digital input buffers disabled . A digital
read of these pins will return ’0’.
CK
I/O pin(1)
N
Data Latch
D
Q
VSS
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
WR
TRIS
Schmitt
Trigger
input
Q
CK
TRIS Latch
buffer
RD TRIS
Q
D
EN
EN
RD PORT
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
1999 Microchip Technology Inc.
Preliminary
DS35008B-page 19
MICROCHIP [ MICROCHIP ]
