PIC16C62B/72A
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
3.2
PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input, (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output, (i.e.,
put the contents of the output latch on the selected pin).
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
FIGURE 3-3: BLOCK DIAGRAM OF
RB3:RB0 PINS
VDD
RBPU(2)
weak
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
P
pull-up
Data Latch
Data Bus
D
Q
I/O
pin(1)
WR Port
CK
TRIS Latch
RB0/INT is an external interupt pin and is configured
using the INTEDG bit (OPTION_REG<6>). RB0/INT is
discussed in detail in Section 10.10.1.
D
Q
TTL
Input
Buffer
WR TRIS
CK
FIGURE 3-4: BLOCK DIAGRAM OF
RB7:RB4 PINS
VDD
RD TRIS
RD Port
RBPU(2)
Q
D
weak
P
pull-up
Data Latch
Data Bus
EN
D
Q
I/O
pin(1)
WR Port
RB0/INT
CK
TRIS Latch
Schmitt Trigger
Buffer
RD Port
D
Q
Note 1: I/O pins have diode protection to VDD and VSS.
WR TRIS
TTL
Input
Buffer
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
CK
ST
Buffer
RD TRIS
RD Port
Latch
Q
Q
D
EN
Q1
Set RBIF
D
From other
RB7:RB4 pins
RD Port
Q3
EN
RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
1999 Microchip Technology Inc.
Preliminary
DS35008B-page 21
MICROCHIP [ MICROCHIP ]
