PIC16C62B/72A
FIGURE 13-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb IN
74
LSb IN
NOTE: Refer to Figure 13-4 for load conditions.
TABLE 13-10: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param. Symbol
No.
Characteristic
Min
Typ† Max Units Conditions
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
TssL2scL
71
TscH
TscL
TB2B
SCK input high time
(slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
40
—
—
—
—
—
—
—
—
—
—
ns
71A
72
ns Note 1
ns
SCK input low time
(slave mode)
1.25TCY + 30
40
72A
73A
ns Note 1
ns Note 1
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
74
75
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
—
—
ns
PIC16CXX
TdoR
SDO data output rise
time
10
20
10
—
10
20
10
—
—
—
—
—
25
45
25
50
25
45
25
50
100
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC16LCXX
76
77
78
TdoF
SDO data output fall time
—
TssH2doZ SS↑ to SDO output hi-impedance
10
PIC16CXX
TscR
SCK output rise time
(master mode)
—
PIC16LCXX
—
79
80
TscF
SCK output fall time (master mode)
—
PIC16CXX
PIC16LCXX
PIC16CXX
PIC16LCXX
TscH2doV, SDO data output valid
TscL2doV after SCK edge
—
—
82
83
TssL2doV SDO data output valid
—
—
after SS↓ edge
TscH2ssH, SS ↑ after SCK edge
1.5TCY + 40
TscL2ssH
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS35008B-page 98
Preliminary
1998 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
