PIC16C62B/72A
FIGURE 13-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
BIT6 - - - - - -1
LSb
SDO
SDI
77
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 13-4 for load conditions.
TABLE 13-9: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param. Symbol
No.
Characteristic
Min
Typ† Max Units Conditions
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
TssL2scL
71
TscH
TscL
SCK input high time
(slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
—
—
—
—
ns
71A
72
40
1.25TCY + 30
40
ns Note 1
SCK input low time
(slave mode)
ns
72A
73
ns Note 1
ns
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
—
—
—
—
ns Note 1
ns
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75
PIC16CXX
TdoR
SDO data output rise time
10
20
10
—
10
20
10
—
—
—
25
45
25
50
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC16LCXX
76
77
78
TdoF
SDO data output fall time
—
10
—
TssH2doZ SS↑ to SDO output hi-impedance
PIC16CXX
TscR
SCK output rise time
(master mode)
PIC16LCXX
79
80
TscF
SCK output fall time (master mode)
—
—
PIC16CXX
TscH2doV, SDO data output valid
TscL2doV after SCK edge
PIC16LCXX
83
TscH2ssH, SS ↑ after SCK edge
1.5TCY + 40
TscL2ssH
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
1998 Microchip Technology Inc.
Preliminary
DS35008B-page 97
MICROCHIP [ MICROCHIP ]
