PIC16C62B/72A
FIGURE 13-17: A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
134
(Tosc/2) (1)
131
130
Q4
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This
allows the SLEEPinstruction to be executed.
TABLE 13-14: A/D CONVERSION REQUIREMENTS
Param Sym
No.
Characteristic
Min
Typ†
Max
Unit
s
Conditions
130
PIC16CXX
PIC16LCXX
PIC16CXX
PIC16LCXX
TAD A/D clock period
1.6
2.0
2.0
3.0
11
—
—
—
—
µs TOSC based, VREF ≥ 3.0V
µs TOSC based, VREF full range
µs A/D RC Mode
4.0
6.0
—
6.0
9.0
11
µs A/D RC Mode
131
132
TCNV Conversion time (not including S/H
TAD
time) (Note 1)
TACQ Acquisition time
Note 2
5*
20
—
—
—
µs
µs The minimum time is the
amplifier settling time. This
may be used if the "new" input
voltage has not changed by
more than 1 LSb (i.e., 20.0 mV
@ 5.12V) from the last sam-
pled voltage (as stated on
CHOLD).
134
TGO
Q4 to A/D clock start
—
TOSC/2
—
—
—
If the A/D clock source is
selected as RC, a time of TCY
is added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
135
Tswc Switching from convert → sample
1.5
—
TAD
time
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 9.1 for min conditions.
DS35008B-page 102
Preliminary
1998 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
