PIC16C62B/72A
The peripheral interrupt flags are contained in the spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
10.10 Interrupts
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
Note: Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupts, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source of the interrupt can be determined by polling the
interrupt flag bits. The interrupt flag bit must be cleared
in software before re-enabling interrupts to avoid recur-
sive interrupts.
A global interrupt enable bit, GIE (INTCON<7>)
enables or disables all interrupts. When bit GIE is
enabled, and an interrupt’s flag bit and mask bit are set,
the interrupt will vector immediately. Individual inter-
rupts can be disabled through their corresponding
enable bits in various registers. Individual interrupt flag
bits are set regardless of the status of the GIE bit. The
GIE bit is cleared on reset.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles, depending on when the
interrupt event occurs. The latency is the same for one
or two cycle instructions. Individual interrupt flag bits
are set regardless of the status of their corresponding
mask bit or the GIE bit
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit, which re-
enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
FIGURE 10-7: INTERRUPT LOGIC
Wake-up (If in SLEEP mode)
Interrupt to CPU
T0IF
T0IE
INTF
INTE
ADIF(1)
ADIE(1)
RBIF
RBIE
SSPIF
SSPIE
PEIE
GIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
Note 1: The A/D module is not implemented on the PIC16C62B.
DS35008B-page 62
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
