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PIC16C62B-04/SO 参数 Datasheet PDF下载

PIC16C62B-04/SO图片预览
型号: PIC16C62B-04/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28引脚8位CMOS微控制器 [28-Pin 8-Bit CMOS Microcontrollers]
分类和应用: 微控制器外围集成电路光电二极管PC可编程只读存储器时钟
文件页数/大小: 120 页 / 1994 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16C62B/72A  
10.10.1 INT INTERRUPT  
10.11 Context Saving During Interrupts  
The external interrupt on RB0/INT pin is edge trig-  
gered: either rising, if bit INTEDG (OPTION_REG<6>)  
is set, or falling, if the INTEDG bit is clear. When a valid  
edge appears on the RB0/INT pin, flag bit INTF  
(INTCON<1>) is set. This interrupt can be disabled by  
clearing enable bit INTE (INTCON<4>). Flag bit INTF  
must be cleared in software in the interrupt service rou-  
tine before re-enabling this interrupt. The INT interrupt  
can wake-up the processor from SLEEP, if bit INTE was  
set prior to going into SLEEP. The status of global inter-  
rupt enable bit GIE decides whether or not the proces-  
sor branches to the interrupt vector following wake-up.  
See Section 10.13 for details on SLEEP mode.  
During an interrupt, only the return PC value is saved  
on the stack. Typically, users may wish to save key reg-  
isters during an interrupt, (i.e., W register and STATUS  
register). This will have to be implemented in software.  
Example 10-1 stores and restores the W and STATUS  
registers. The register, W_TEMP, must be defined in  
each bank and must be defined at the same offset from  
the bank base address (i.e., if W_TEMP is defined at  
0x20 in bank 0, it must also be defined at 0xA0 in bank  
1).  
The example:  
a) Stores the W register.  
b) Stores the STATUS register in bank 0.  
c) Stores the PCLATH register.  
10.10.2 TMR0 INTERRUPT  
An overflow (FFh 00h) in the TMR0 register will set  
flag bit T0IF (INTCON<2>). The interrupt can be  
enabled/disabled by setting/clearing enable bit T0IE  
(INTCON<5>). (Section 4.0)  
d) Executes the interrupt service routine code  
(User-generated).  
e) Restores the STATUS register (and bank select  
bit).  
f) Restores the W and PCLATH registers.  
10.10.3 PORTB INTCON CHANGE  
An input change on PORTB<7:4> sets flag bit RBIF  
(INTCON<0>). The interrupt can be enabled/disabled  
by setting/clearing enable bit RBIE (INTCON<4>).  
(Section 3.2)  
EXAMPLE 10-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM  
MOVWF  
SWAPF  
CLRF  
MOVWF  
:
W_TEMP  
STATUS,W  
STATUS  
;Copy W to TEMP register, could be bank one or zero  
;Swap status to be saved into W  
;bank 0, regardless of current bank, Clears IRP,RP1,RP0  
;Save status to bank zero STATUS_TEMP register  
STATUS_TEMP  
:(ISR)  
:
SWAPF  
STATUS_TEMP,W  
;Swap STATUS_TEMP register into W  
;(sets bank to original state)  
;Move W into STATUS register  
;Swap W_TEMP  
MOVWF  
SWAPF  
SWAPF  
STATUS  
W_TEMP,F  
W_TEMP,W  
;Swap W_TEMP into W  
1999 Microchip Technology Inc.  
Preliminary  
DS35008B-page 63  
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