PIC16C62B/72A
other is the Power-up Timer (PWRT), which provides a
fixed delay on power-up only and is designed to keep
the part in reset while the power supply stabilizes. With
these two timers on-chip, most applications need no
external reset circuitry.
10.0 SPECIAL FEATURES OF THE
CPU
The PIC16C62B/72A devices have a host of features
intended to maximize system reliability, minimize cost
through elimination of external components, provide
power saving operating modes and offer code protec-
tion. These are:
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
• Oscillator Mode Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
Additional information on special features is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
• Watchdog Timer (WDT)
• SLEEP
10.1
Configuration Bits
• Code protection
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
• ID locations
• In-circuit serial programming™ (ICSP)
These devices have a Watchdog Timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in reset until the crystal oscillator is stable. The
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h -
3FFFh), which can be accessed only during program-
ming.
FIGURE 10-1: CONFIGURATION WORD
CP1 CP0 CP1 CP0 CP1 CP0
—
BODEN CP1 CP0 PWRTE WDTE
FOSC1 FOSC0
bit0
Register: CONFIG
Address: 2007h
bit13
(2)
bit 13-8 CP1:CP0: Code Protection bits
5-4: 11= Code protection off
10= Upper half of program memory code protected
01= Upper 3/4th of program memory code protected
00= All memory is code protected
bit 7:
bit 6:
Unimplemented: Read as ’1’
(1)
BODEN: Brown-out Reset Enable bit
1= BOR enabled
0= BOR disabled
(1)
bit 3:
bit 2:
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE.
All of the CP1:CP0 pairs must be given the same value to enable the code protection scheme listed.
1999 Microchip Technology Inc.
Preliminary
DS35008B-page 55
MICROCHIP [ MICROCHIP ]
