PIC12F635/PIC16F636/639
8-Pin Diagrams (PDIP, SOIC, DFN, DFN-S)
PDIP, SOIC
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
1
2
VSS
8
7
GP0/C1IN+/ICSPDAT/ULPWU
GP1/C1IN-/ICSPCLK
GP2/T0CKI/INT/C1OUT
3
4
6
5
DFN, DFN-S
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/T1G/OSC2/CLKOUT
GP3/MCLR/VDD
VSS
8
7
6
5
1
2
GP0/CIN+/ICSPDAT/ULPWU
GP1/CIN-/ICSPCLK
GP2/T0CKI/INT/COUT
3
4
TABLE 1:
I/O
8-PIN SUMMARY (PDIP, SOIC, DFN, DFN-S)
Pin
Comparators
Timer
Interrupts
Pull-ups
Basic
GP0
7
6
5
C1IN+
C1IN-
—
—
IOC
IOC
Y
Y
Y
ICSPDAT/ULPWU
GP1
ICSPCLK
—
GP2
C1OUT
T0CKI
INT/IOC
GP3(1)
4
3
2
1
8
—
—
—
—
—
—
T1G
T1CKI
—
IOC
IOC
IOC
—
Y(2)
Y
MCLR/VPP
OSC2/CLKOUT
OSC1/CLKIN
VDD
GP4
GP5
—
Y
—
—
—
—
—
VSS
Note 1: Input only.
2: Only when pin is configured for external MCLR.
© 2007 Microchip Technology Inc.
DS41232D-page 3
MICROCHIP [ MICROCHIP ]
