PIC12F635/PIC16F636/639
FIGURE 12-8:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(3)
CLKOUT
(4)
INT pin
(1)
(1)
(5)
(2)
Interrupt Latency
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
0004h
PC + 1
PC + 1
—
0005h
Inst (0005h)
Inst (0004h)
PC
Instruction
Fetched
Inst (PC)
Inst (PC + 1)
Inst (0004h)
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC – 1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Value on
Value on:
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
INTCON
IOCA
PIR1
GIE
—
PEIE
—
T0IE
INTE
RAIE
T0IF
INTF
IOCA1
—
RAIF
0000 000x 0000 000x
IOCA5 IOCA4 IOCA3 IOCA2
CRIF C2IF(1) C1IF OSFIF
CRIE C2IE(1) C1IE OSFIE
IOCA0 --00 0000 --00 0000
TMR1IF 0000 00-0 0000 00-0
TMR1IE 0000 00-0 0000 00-0
EEIF
EEIE
LVDIF
LVDIE
PIE1
—
Legend: x= unknown, u= unchanged, – = unimplemented, read as ‘0’, q= value depends upon condition.
Shaded cells are not used by the Interrupt module.
Note 1: PIC16F636/639 only.
© 2007 Microchip Technology Inc.
DS41232D-page 141
MICROCHIP [ MICROCHIP ]
