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PIC12F635-I/SN 参数 Datasheet PDF下载

PIC12F635-I/SN图片预览
型号: PIC12F635-I/SN
PDF下载: 下载PDF文件 查看货源
内容描述: 8月14日引脚,基于闪存的8位CMOS微控制器采用纳瓦技术 [8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 234 页 / 3856 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC12F635/PIC16F636/639  
If the filter resets due to a long high (TOEH > TOET), the  
high-pulse timer will not begin timing again until after a  
gap of TE and another low-to-high transition occurs on  
TABLE 11-1: TYPICAL OUTPUT ENABLE  
FILTER TIMING  
OEH  
OEL  
TOEH  
(ms)  
TOEL  
(ms)  
TOET  
the demodulator output.  
<1:0>  
<1:0>  
(ms)  
Disabling the output enable filter disables the TOEH and  
TOEL requirement and the AFE passes all received LF  
data. See Figure 11-10, Figure 11-11 and Figure 11-12  
for examples.  
01  
01  
01  
01  
00  
01  
10  
11  
1
1
1
1
1
1
2
4
3
3
4
6
When viewed from an application perspective, from the  
pin input, the actual output enable filter timing must fac-  
tor in the analog delays in the input path (such as  
demodulator charge and discharge times).  
10  
10  
10  
10  
00  
01  
10  
11  
2
2
2
2
1
1
2
4
4
4
5
8
TOEH - TDR + TDF  
TOEL + TDR - TDF  
The output enable filter starts immediately after TGAP,  
the gap after AGC stabilization period.  
11  
11  
11  
11  
00  
01  
10  
11  
4
4
4
4
1
1
2
4
6
6
11.16 Input Sensitivity Control  
8
10  
The AFE is designed to have typical input sensitivity of  
3 mVPP. This means any input signal with amplitude  
greater than 3 mVPP can be detected. The AFE’s internal  
AGC loop regulates the detecting signal amplitude when  
the input level is greater than approximately 20 mVPP.  
This signal amplitude is called “AGC-active level”. The  
AGC loop regulates the input voltage so that the input  
signal amplitude range will be kept within the linear range  
of the detection circuits without saturation. The AGC  
Active Status bit AGCACT<5>, in the AFE Status  
Register 7 (Register 11-8) is set if the AGC loop  
regulates the input voltage.  
00  
XX  
Filter Disabled  
Note 1: Typical at room temperature and  
VDD = 3.0V, 32 kHz oscillator.  
TOEH is measured from the rising edge of the demodulator  
output to the first falling edge. The pulse width must fall  
within TOEH t TOET.  
TOEL is measured from the falling edge of the  
demodulator output to the rising edge of the next pulse.  
The pulse width must fall within TOEL t TOET.  
Table 11-2 shows the input sensitivity comparison when  
the AGCSIG option is used. When AGCSIG option bit is  
set, the demodulated output is available only when the  
AGC loop is active (see Table 11-1). The AFE has also  
input sensitivity reduction options per each channel. The  
Configuration Register 3 (Register 11-4), Configuration  
Register 4 (Register 11-5) and Configuration Register 5  
(Register 11-6) have the option to reduce the channel  
gains from 0 dB to approximately -30 dB.  
TOET is measured from rising edge to the next rising  
edge (i.e., the sum of TOEH and TOEL). The pulse width  
must be t TOET. If the Configuration Register 0  
(Register 11-1), OEL<8:7> is set to ‘00’, then TOEH  
must not exceed TOET and TOEL must not exceed  
TINACT.  
The filter will reset, requiring a complete new successive  
high and low period to enable LFDATA, under the  
following conditions.  
• The received high is not greater than the  
configured minimum TOEH value.  
• During TOEH, a loss of signal > 56 μs. A loss of  
signal < 56 μs may or may not cause a filter  
Reset.  
• The received low is not greater than the  
configured minimum TOEL value.  
• The received sequence exceeds the maximum  
TOET value:  
- TOEH + TOEL > TOET  
- or TOEH > TOET  
- or TOEL > TOET  
• A Soft Reset SPI command is received.  
© 2007 Microchip Technology Inc.  
DS41232D-page 105  
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