PIC12C5XX
The PIC12C5XX has a Watchdog Timer which can be
shut off only through configuration bit WDTE. It runs
off of its own RC oscillator for added reliability. If using
XT or LP selectable oscillator options, there is always
an 18 ms (nominal) delay provided by the Device
Reset Timer (DRT), intended to keep the chip in reset
until the crystal oscillator is stable. If using INTRC or
EXTRC there is an 18 ms delay only on VDD power-up.
With this timer on-chip, most applications need no
external reset circuitry.
8.0
SPECIAL FEATURES OF THE
CPU
What sets
a
microcontroller apart from other
processors are special circuits to deal with the needs
of real-time applications. The PIC12C5XX family of
microcontrollers has a host of such features intended
to maximize system reliability, minimize cost through
elimination of external components, provide power
saving operating modes and offer code protection.
These features are:
The SLEEP mode is designed to offer a very low
current power-down mode. The user can wake-up
from SLEEP through a change on input pins or
through a Watchdog Timer time-out. Several oscillator
options are also made available to allow the part to fit
the application, including an internal 4 MHz oscillator.
The EXTRC oscillator option saves system cost while
• Oscillator selection
• Reset
- Power-On Reset (POR)
- Device Reset Timer (DRT)
- Wake-up from SLEEP on pin change
• Watchdog Timer (WDT)
• SLEEP
the LP crystal option saves power.
A set of
configuration bits are used to select various options.
• Code protection
8.1
Configuration Bits
• ID locations
• In-circuit Serial Programming
The PIC12C5XX configuration word consists of 12
bits. Configuration bits can be programmed to select
various device configurations. Two bits are for the
selection of the oscillator type, one bit is the Watchdog
Timer enable bit, and one bit is the MCLR enable bit.
FIGURE 8-1:
CONFIGURATION WORD FOR PIC12C5XX
—
—
—
9
—
8
—
7
—
6
—
5
MCLRE CP
WDTE FOSC1 FOSC0
bit0
Register: CONFIG
Address(1)
FFFh
:
bit11
10
4
3
2
1
bit 11-5: Unimplemented
bit 4:
bit 3:
bit 2:
MCLRE: MCLR enable bit.
1 = MCLR pin enabled
0 = MCLR tied to VDD, (Internally)
CP: Code protection bit.
1 = Code protection off
0 = Code protection on
WDTE: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator selection bits
11 = EXTRC - external RC oscillator
10 = INTRC - internal RC oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Refer to the PIC12C5XX Programming Specifications to determine how to access the
configuration word. This register is not user addressable during device operation.
1999 Microchip Technology Inc.
DS40139E-page 35
MICROCHIP [ MICROCHIP ]
