PIC12C5XX
7.0.2
SERIAL CLOCK
7.1.4
DATA VALID (D)
This SCL input is used to synchronize the data transfer
from and to the device.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
7.1
BUS CHARACTERISTICS
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
The following bus protocol is to be used with the
EEPROM data memory.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
• Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as a
START or STOP condition.
7.1.5
ACKNOWLEDGE
Accordingly, the following bus conditions have been
defined (Figure 7-3).
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
7.1.1
Both data and clock lines remain HIGH.
7.1.2 START DATA TRANSFER (B)
BUS NOT BUSY (A)
Note: Acknowledge bits are not generated if an
internal programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 7-4).
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
7.1.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
1999 Microchip Technology Inc.
DS40139E-page 31
MICROCHIP [ MICROCHIP ]
