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PIC12C508A-04/P 参数 Datasheet PDF下载

PIC12C508A-04/P图片预览
型号: PIC12C508A-04/P
PDF下载: 下载PDF文件 查看货源
内容描述: 8引脚, 8位CMOS微控制器 [8-Pin, 8-Bit CMOS Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC可编程只读存储器时钟
文件页数/大小: 113 页 / 1604 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC12C5XX  
7.3  
WRITE OPERATIONS  
7.4  
ACKNOWLEDGE POLLING  
7.3.1  
BYTE WRITE  
Since the device will not acknowledge during a write  
cycle, this can be used to determine when the cycle is  
complete (this feature can be used to maximize bus  
throughput). Once the stop condition for a write com-  
mand has been issued from the master, the device ini-  
tiates the internally timed write cycle. ACK polling can  
be initiated immediately. This involves the master send-  
ing a start condition followed by the control byte for a  
write command (R/W = 0). If the device is still busy with  
the write cycle, then no ACK will be returned. If no ACK  
is returned, then the start bit and control byte must be  
re-sent. If the cycle is complete, then the device will  
return the ACK and the master can then proceed with  
the next read or write command. See Figure 7-6 for  
flow diagram.  
Following the start signal from the master, the device  
code (4 bits), the don’t care bits (3 bits), and the R/W  
bit (which is a logic low) are placed onto the bus by the  
master transmitter. This indicates to the addressed  
slave receiver that a byte with a word address will follow  
after it has generated an acknowledge bit during the  
ninth clock cycle. Therefore, the next byte transmitted  
by the master is the word address and will be written  
into the address pointer. Only the lower four address  
bits are used by the device, and the upper four bits are  
don’t cares. The address byte is acknowledgeable and  
the master device will then transmit the data word to be  
written into the addressed memory location. The mem-  
ory acknowledges again and the master generates a  
stop condition. This initiates the internal write cycle,  
and during this time will not generate acknowledge sig-  
nals (Figure 7-7). After a byte write command, the inter-  
nal address counter will not be incremented and will  
point to the same address location that was just written.  
If a stop bit is transmitted to the device at any point in  
the write command sequence before the entire  
sequence is complete, then the command will abort  
and no data will be written. If more than 8 data bits are  
transmitted before the stop bit is sent, then the device  
will clear the previously loaded byte and begin loading  
the data buffer again. If more than one data byte is  
transmitted to the device and a stop bit is sent before a  
full eight data bits have been transmitted, then the write  
command will abort and no data will be written. The  
EEPROM memory employs a VCC threshold detector  
circuit which disables the internal erase/write logic if the  
VCC is below minimum VDD.  
FIGURE 7-6: ACKNOWLEDGE POLLING  
FLOW  
Send  
Write Command  
Send Stop  
Condition to  
Initiate Write Cycle  
Send Start  
Send Control Byte  
with R/W = 0  
Byte write operations must be preceded and immedi-  
ately followed by a bus not busy bus cycle where both  
SDA and SCL are held high.  
Did Device  
NO  
Acknowledge  
(ACK = 0)?  
YES  
Next  
Operation  
FIGURE 7-7: BYTE WRITE  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY  
MASTER  
CONTROL  
BYTE  
WORD  
ADDRESS  
DATA  
SDA LINE  
P
S
1
0
1
0
X
X
X
0
X
X
X
X
A
C
K
A
C
K
A
C
K
BUS ACTIVITY  
X = Don’t Care Bit  
1999 Microchip Technology Inc.  
DS40139E-page 33  
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