PIC12F629/675
FIGURE 9-12:
WATCHDOG TIMER BLOCK DIAGRAM
CLKOUT
(= FOSC/4)
Data Bus
0
8
1
0
SYNC 2
Cycles
1
TMR0
T0CKI
pin
0
Set Flag bit T0IF
on Overflow
T0CS
T0SE
8-bit
Prescaler
PSA
1
8
PSA
1
0
PS0 - PS2
WDT
Time-out
Watchdog
Timer
PSA
WDTE
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
TABLE 9-9:
SUMMARY OF WATCHDOG TIMER REGISTERS
Value on all
other
Resets
Value on
POR, BOD
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
81h
OPTION_REG GPPU INTEDG T0CS
Config. bits CP
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
2007h
BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 uuuu uuuu uuuu uuuu
Legend: u= Unchanged, shaded cells are not used by the Watchdog Timer.
2010 Microchip Technology Inc.
DS41190G-page 67
MICROCHIP [ MICROCHIP ]
