PIC12F629/675
9.4.1
GP2/INT INTERRUPT
9.4.3
GPIO INTERRUPT
External interrupt on GP2/INT pin is edge-triggered;
either rising if INTEDG bit (OPTION<6>) is set, of
falling, if INTEDG bit is clear. When a valid edge
appears on the GP2/INT pin, the INTF bit (INT-
CON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The GP2/INT
interrupt can wake-up the processor from Sleep if the
INTE bit was set prior to going into Sleep. The status of
the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 9.7 “Power-Down Mode (Sleep)” for details
on Sleep and Figure 9-13 for timing of wake-up from
Sleep through GP2/INT interrupt.
An input change on GPIO change sets the GPIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the GPIE (INTCON<3>)
bit. Plus individual pins can be configured through the
IOC register.
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF
interrupt flag may not get set.
9.4.4
COMPARATOR INTERRUPT
See Section 6.9 “Comparator Interrupts” for
description of comparator interrupt.
9.4.5
A/D CONVERTER INTERRUPT
Note: The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
The ANSEL register is defined for the
PIC12F675.
After a conversion is complete, the ADIF flag (PIR<6>)
is set. The interrupt can be enabled/disabled by setting
or clearing ADIE (PIE<6>).
See Section 7.0 “Analog-to-Digital Converter (A/D)
Module (PIC12F675 only)” for operation of the A/D
converter interrupt.
9.4.2
TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 4.0 “Timer0 Module”.
FIGURE 9-11:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
3
4
INT pin
1
1
Interrupt Latency
INTF Flag
(INTCON<1>)
5
2
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC + 1
—
0004h
0005h
PC
PC + 1
Instruction
Fetched
Inst (PC+1)
Inst (0004h)
Inst (PC)
Inst (0005h)
Inst (0004h)
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC - 1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
2010 Microchip Technology Inc.
DS41190G-page 65
MICROCHIP [ MICROCHIP ]
