PIC10F200/202/204/206
FIGURE 9-6:
WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 6-5)
0
M
U
X
Postscaler
8-to-1 MUX
1
Watchdog
Time
PS<2:0>
PSA
WDT Enable
Configuration
(Figure 6-4)
To Timer0
Bit
0
1
MUX
PSA
WDT Time-out
TABLE 9-4:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on
Value on
All Other
Resets
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On
Reset
N/A
OPTION
GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer, – = unimplemented, read as ‘0’, u= unchanged.
© 2007 Microchip Technology Inc.
DS41239D-page 47
MICROCHIP [ MICROCHIP ]
