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PIC10F204T-I/OT 参数 Datasheet PDF下载

PIC10F204T-I/OT图片预览
型号: PIC10F204T-I/OT
PDF下载: 下载PDF文件 查看货源
内容描述: 6引脚8位闪存微控制器 [6-Pin, 8-Bit Flash Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 96 页 / 1447 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC10F200/202/204/206  
TABLE 9-2:  
RESET CONDITION FOR SPECIAL REGISTERS  
STATUS Addr: 03h  
PCL Addr: 02h  
Power-on Reset  
00-1 1xxx  
000u uuuu  
0001 0uuu  
0000 0uuu  
0000 uuuu  
1001 0uuu  
0101 0uuu  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
MCLR Reset during normal operation  
MCLR Reset during Sleep  
WDT Reset during Sleep  
WDT Reset normal operation  
Wake-up from Sleep on pin change  
Wake-up from Sleep on comparator change  
Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’.  
The Power-on Reset circuit and the Device Reset  
Timer (see Section 9.5 “Device Reset Timer (DRT)”)  
circuit are closely related. On power-up, the Reset latch  
is set and the DRT is reset. The DRT timer begins  
counting once it detects MCLR to be high. After the  
time-out period, which is typically 18 ms, it will reset the  
Reset latch and thus end the on-chip Reset signal.  
9.3.1  
MCLR ENABLE  
This Configuration bit, when unprogrammed (left in the  
1’ state), enables the external MCLR function. When  
programmed, the MCLR function is tied to the internal  
VDD and the pin is assigned to be a I/O. See Figure 9-1.  
FIGURE 9-1:  
MCLR SELECT  
A power-up example where MCLR is held low is shown  
in Figure 9-3. VDD is allowed to rise and stabilize before  
bringing MCLR high. The chip will actually come out of  
Reset TDRT msec after MCLR goes high.  
GPWU  
In Figure 9-4, the on-chip Power-on Reset feature is  
being used (MCLR and VDD are tied together or the pin  
is programmed to be GP3). The VDD is stable before  
the Start-up Timer times out and there is no problem in  
getting a proper Reset. However, Figure 9-5 depicts a  
problem situation where VDD rises too slowly. The time  
between when the DRT senses that MCLR is high and  
when MCLR and VDD actually reach their full value, is  
too long. In this situation, when the Start-up Timer times  
out, VDD has not reached the VDD (min) value and the  
chip may not function correctly. For such situations, we  
recommend that external RC circuits be used to  
achieve longer POR delay times (Figure 9-4).  
GP3/MCLR/VPP  
Internal MCLR  
MCLRE  
9.4  
Power-on Reset (POR)  
The PIC10F200/202/204/206 devices incorporate an  
on-chip Power-on Reset (POR) circuitry, which  
provides an internal chip Reset for most power-up  
situations.  
The on-chip POR circuit holds the chip in Reset until  
VDD has reached a high enough level for proper oper-  
ation. To take advantage of the internal POR, program  
the GP3/MCLR/VPP pin as MCLR and tie through a  
resistor to VDD, or program the pin as GP3. An internal  
weak pull-up resistor is implemented using a transistor  
(refer to Table 12-2 for the pull-up resistor ranges).  
This will eliminate external RC components usually  
needed to create a Power-on Reset. A maximum rise  
time for VDD is specified. See Section 12.0 “Electrical  
Characteristics” for details.  
Note:  
When the devices start normal operation  
(exit the Reset condition), device operat-  
ing parameters (voltage, frequency,  
temperature, etc.) must be met to ensure  
operation. If these conditions are not met,  
the device must be held in Reset until the  
operating conditions are met.  
For additional information, refer to Application Notes  
AN522 “Power-Up Considerations”, (DS00522) and  
AN607 “Power-up Trouble Shooting”, (DS00607).  
When the devices start normal operation (exit the  
Reset condition), device operating parameters (volt-  
age, frequency, temperature,...) must be met to ensure  
operation. If these conditions are not met, the devices  
must be held in Reset until the operating parameters  
are met.  
A simplified block diagram of the on-chip Power-on  
Reset circuit is shown in Figure 9-2.  
© 2007 Microchip Technology Inc.  
DS41239D-page 43