PIC10F200/202/204/206
9.7
Time-out Sequence, Power-down
and Wake-up from Sleep Status
Bits (TO, PD, GPWUF, CWUF)
The TO, PD, GPWUF and CWUF bits in the STATUS
register can be tested to determine if a Reset condition
has been caused by a power-up condition, a MCLR,
Watchdog Timer (WDT) Reset, wake-up on comparator
change or wake-up on pin change.
TABLE 9-5:
CWUF
TO, PD, GPWUF, CWUF STATUS AFTER RESET
GPWUF
TO
PD
Reset Caused By
WDT wake-up from Sleep
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
1
u
1
1
0
u
0
1
u
0
0
WDT time-out (not from Sleep)
MCLR wake-up from Sleep
Power-up
MCLR not during Sleep
Wake-up from Sleep on pin change
Wake-up from Sleep on comparator change
Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’, q= value depends on condition.
Note 1: The TO, PD, GPWUF and CWUF bits maintain their status (u) until a Reset occurs. A low-pulse on the
MCLR input does not change the TO, PD, GPWUF or CWUF Status bits.
FIGURE 9-8:
BROWN-OUT
9.8
Reset on Brown-out
PROTECTION CIRCUIT 2
A Brown-out Reset is a condition where device power
(VDD) dips below its minimum value, but not to zero,
and then recovers. The device should be reset in the
event of a brown-out.
VDD
VDD
R1
R2
To reset PIC10F200/202/204/206 devices when a
Brown-out Reset occurs, external brown-out protection
circuits may be built, as shown in Figure 9-7 and
Figure 9-8.
PIC10F20X
Q1
(2)
MCLR
(1)
40k
FIGURE 9-7:
BROWN-OUT
PROTECTION CIRCUIT 1
VDD
Note 1: This brown-out circuit is less expensive,
although less accurate. Transistor Q1 turns
off when VDD is below a certain level such
VDD
33k
that:
R1
R1 + R2
= 0.7V
VDD •
PIC10F20X
Q1
(2)
MCLR
10k
(1)
2: Pin must be confirmed as MCLR.
40k
Note 1: This circuit will activate Reset when VDD goes
below Vz + 0.7V (where Vz = Zener voltage).
2: Pin must be confirmed as MCLR.
DS41239D-page 48
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
