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FIGURE 9-6:
WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
0
Watchdog
Time
1
M
U
X
Postscaler
8-to-1 MUX
WDT Enable
Configuration
Bit
PSA
PS<2:0>
To Timer0 (Figure 6-4)
0
MUX
1
PSA
WDT Time-out
TABLE 9-4:
Address
N/A
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Name
Bit 7
GPWU
Bit 6
GPPU
Bit 5
T0CS
Bit 4
T0SE
Bit 3
PSA
Bit 2
PS2
Bit 1 Bit 0
PS1
PS0
Value on
Power-On
Reset
1111 1111
Value on
All Other
Resets
1111 1111
OPTION
Legend:
Shaded boxes = Not used by Watchdog Timer, – = unimplemented, read as ‘0’,
u
= unchanged.
©
2007 Microchip Technology Inc.
DS41239D-page 47