PIC10F200/202/204/206
TABLE 9-2:
Power-on Reset
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset during Sleep
WDT Reset normal operation
Wake-up from Sleep on pin change
Wake-up from Sleep on comparator change
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h
00-1 1xxx
000u uuuu
0001 0uuu
0000 0uuu
0000 uuuu
1001 0uuu
0101 0uuu
PCL Addr: 02h
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
Legend:
u
= unchanged,
x
= unknown, – = unimplemented bit, read as ‘0’.
9.3.1
MCLR ENABLE
This Configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
V
DD
and the pin is assigned to be a I/O. See Figure 9-1.
FIGURE 9-1:
GPWU
MCLR SELECT
The Power-on Reset circuit and the Device Reset
Timer (see
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, which is typically 18 ms, it will reset the
Reset latch and thus end the on-chip Reset signal.
A power-up example where MCLR is held low is shown
in Figure 9-3. V
DD
is allowed to rise and stabilize before
bringing MCLR high. The chip will actually come out of
Reset T
DRT
msec after MCLR goes high.
In Figure 9-4, the on-chip Power-on Reset feature is
being used (MCLR and V
DD
are tied together or the pin
is programmed to be GP3). The V
DD
is stable before
the Start-up Timer times out and there is no problem in
getting a proper Reset. However, Figure 9-5 depicts a
problem situation where V
DD
rises too slowly. The time
between when the DRT senses that MCLR is high and
when MCLR and V
DD
actually reach their full value, is
too long. In this situation, when the Start-up Timer times
out, V
DD
has not reached the V
DD
(min) value and the
chip may not function correctly. For such situations, we
recommend that external RC circuits be used to
achieve longer POR delay times (Figure 9-4).
Note:
When the devices start normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency,
temperature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
GP3/MCLR/V
PP
MCLRE
Internal MCLR
9.4
Power-on Reset (POR)
The PIC10F200/202/204/206 devices incorporate an
on-chip Power-on Reset (POR) circuitry, which
provides an internal chip Reset for most power-up
situations.
The on-chip POR circuit holds the chip in Reset until
V
DD
has reached a high enough level for proper oper-
ation. To take advantage of the internal POR, program
the GP3/MCLR/V
PP
pin as MCLR and tie through a
resistor to V
DD
, or program the pin as GP3. An internal
weak pull-up resistor is implemented using a transistor
(refer to Table 12-2 for the pull-up resistor ranges).
This will eliminate external RC components usually
needed to create a Power-on Reset. A maximum rise
time for V
DD
is specified. See
for details.
When the devices start normal operation (exit the
Reset condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 9-2.
For additional information, refer to Application Notes
AN522
“Power-Up Considerations”,
(DS00522) and
AN607
“Power-up Trouble Shooting”,
(DS00607).
©
2007 Microchip Technology Inc.
DS41239D-page 43
MICROCHIP [ MICROCHIP TECHNOLOGY ]
