MCP41XXX/42XXX
2.1
Parametric Test Circuits
VA
V+ = VDD
1LSB = V+/256
A
VDD
A
V+
V+
W
W
B
B
DUT
+
-
DUT
+
-
VMEAS
*
VMEAS
*
*Assume infinite input impedance
V+ = VDD ± 10%
FIGURE 2-25:
Potentiometer Divider Non-
∆VDD
PSRR (dB) = 20LOG
(
)
Linearity Error Test Circuit (DNL, INL).
∆VMEAS
PSS (%/%) = ∆VDD
∆VMEAS
No Connection
*Assume infinite input impedance
FIGURE 2-28:
Power Supply Sensitivity
A
IW
Test Circuit (PSS, PSRR).
W
B
DUT
+
-
A
VMEAS
*
+5V
W
VIN
VOUT
+
~
-
*Assume infinite input impedance
OFFSET
GND
DUT
B
FIGURE 2-26:
Resistor Position Non-
Linearity Error Test Circuit (Rheostat operation
DNL, INL).
2.5V DC
Rsw = 0.1V
Isw
FIGURE 2-29:
Gain vs. Frequency Test
Circuit.
A
Code = 00h
W
DUT
DUT
B
+
-
ISW
B
A
0.1V
+5V
VSS = 0 to VDD
VOUT
-
+
VIN
~
MCP601
2.5V DC
Offset
FIGURE 2-27:
Wiper Resistance Test
Circuit.
FIGURE 2-30:
Capacitance Test Circuit.
2003 Microchip Technology Inc.
DS11195C-page 11
MICROCHIP [ MICROCHIP ]
