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MCP4162T-502E/SN 参数 Datasheet PDF下载

MCP4162T-502E/SN图片预览
型号: MCP4162T-502E/SN
PDF下载: 下载PDF文件 查看货源
内容描述: 7/8位单/双SPI数字电位器具有非易失性存储器 [7/8-Bit Single/Dual SPI Digital POT with Non-Volatile Memory]
分类和应用: 转换器电位器数字电位计存储电阻器光电二极管
文件页数/大小: 88 页 / 2259 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号MCP4162T-502E/SN的Datasheet PDF文件第42页浏览型号MCP4162T-502E/SN的Datasheet PDF文件第43页浏览型号MCP4162T-502E/SN的Datasheet PDF文件第44页浏览型号MCP4162T-502E/SN的Datasheet PDF文件第45页浏览型号MCP4162T-502E/SN的Datasheet PDF文件第47页浏览型号MCP4162T-502E/SN的Datasheet PDF文件第48页浏览型号MCP4162T-502E/SN的Datasheet PDF文件第49页浏览型号MCP4162T-502E/SN的Datasheet PDF文件第50页  
MCP414X/416X/424X/426X  
TABLE 7-2:  
MEMORY MAP AND THE SUPPORTED COMMANDS  
Address  
SPI String (Binary)  
Data  
Command  
(10-bits) (1)  
Value  
Function  
MOSI (SDI pin)  
MISO (SDO pin) (2)  
00h  
Volatile Wiper 0  
Write Data  
nn nnnn nnnn  
nn nnnn nnnn  
0000 00nn nnnn nnnn  
0000 11nn nnnn nnnn  
0000 0100  
1111 1111 1111 1111  
1111 111n nnnn nnnn  
1111 1111  
Read Data  
Increment Wiper  
Decrement Wiper  
Write Data  
0000 1000  
1111 1111  
01h  
02h  
03h  
Volatile Wiper 1  
NV Wiper 0  
nn nnnn nnnn  
nn nnnn nnnn  
0001 00nn nnnn nnnn  
0001 11nn nnnn nnnn  
0001 0100  
1111 1111 1111 1111  
1111 111n nnnn nnnn  
1111 1111  
Read Data  
Increment Wiper  
Decrement Wiper  
Write Data  
0001 1000  
1111 1111  
nn nnnn nnnn  
nn nnnn nnnn  
0010 00nn nnnn nnnn  
0010 11nn nnnn nnnn  
0010 0100  
1111 1111 1111 1111  
1111 111n nnnn nnnn  
1111 1111  
Read Data  
HV Inc. (WL0 DIS) (3)  
HV Dec. (WL0 EN) (4)  
Write Data  
0010 1000  
1111 1111  
NV Wiper 1  
nn nnnn nnnn  
nn nnnn nnnn  
0011 00nn nnnn nnnn  
0011 11nn nnnn nnnn  
0011 0100  
1111 1111 1111 1111  
1111 111n nnnn nnnn  
1111 1111  
Read Data  
HV Inc. (WL1 DIS) (3)  
HV Dec. (WL1 EN) (4)  
Write Data  
0011 1000  
1111 1111  
04h (5) Volatile  
TCON Register  
05h (5) Status Register  
06h (5) Data EEPROM  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
nn nnnn nnnn  
0100 00nn nnnn nnnn  
0100 11nn nnnn nnnn  
0101 11nn nnnn nnnn  
0110 00nn nnnn nnnn  
0110 11nn nnnn nnnn  
0111 00nn nnnn nnnn  
0111 11nn nnnn nnnn  
1000 00nn nnnn nnnn  
1000 11nn nnnn nnnn  
1001 00nn nnnn nnnn  
1001 11nn nnnn nnnn  
1010 00nn nnnn nnnn  
1010 11nn nnnn nnnn  
1011 00nn nnnn nnnn  
1011 11nn nnnn nnnn  
1100 00nn nnnn nnnn  
1100 11nn nnnn nnnn  
1101 00nn nnnn nnnn  
1101 11nn nnnn nnnn  
1110 00nn nnnn nnnn  
1110 11nn nnnn nnnn  
1111 00nn nnnn nnnn  
1111 11nn nnnn nnnn  
1111 0100  
1111 1111 1111 1111  
1111 111n nnnn nnnn  
1111 111n nnnn nnnn  
1111 1111 1111 1111  
1111 111n nnnn nnnn  
1111 1111 1111 1111  
1111 111n nnnn nnnn  
1111 1111 1111 1111  
1111 111n nnnn nnnn  
1111 1111 1111 1111  
1111 111n nnnn nnnn  
1111 1111 1111 1111  
1111 111n nnnn nnnn  
1111 1111 1111 1111  
1111 111n nnnn nnnn  
1111 1111 1111 1111  
1111 111n nnnn nnnn  
1111 1111 1111 1111  
1111 111n nnnn nnnn  
1111 1111 1111 1111  
1111 111n nnnn nnnn  
1111 1111 1111 1111  
1111 111n nnnn nnnn  
1111 1111  
Read Data  
Read Data  
Write Data  
Read Data  
07h (5) Data EEPROM  
08h (5) Data EEPROM  
09h (5) Data EEPROM  
0Ah (5) Data EEPROM  
0Bh (5) Data EEPROM  
0Ch (5) Data EEPROM  
0Dh (5) Data EEPROM  
0Eh (5) Data EEPROM  
Write Data  
Read Data  
Write Data  
Read Data  
Write Data  
Read Data  
Write Data  
Read Data  
Write Data  
Read Data  
Write Data  
Read Data  
Write Data  
Read Data  
Write Data  
Read Data  
0Fh  
Data EEPROM  
Write Data  
Read Data  
HV Inc. (WP DIS) (3)  
HV Dec. (WP EN) (4)  
1111 1000  
1111 1111  
Note 1: The Data Memory is only 9-bits wide, so the MSb is ignored by the device.  
2: All these Address/Command combinations are valid, so the CMDERR bit is set. Any other Address/Command combi-  
nation is a command error state and the CMDERR bit will be clear.  
3: Disables WiperLock Technology for wiper 0 or wiper 1, or disables Write Protect.  
4: Enables WiperLock Technology for wiper 0 or wiper 1, or enables Write Protect.  
5: Reserved addresses: Increment or Decrement commands are invalid for these addresses.  
DS22059B-page 46  
© 2008 Microchip Technology Inc.  
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