MCP2021/2
2.5
Timing Diagrams and Specifications
FIGURE 2-4:
BUS TIMING DIAGRAM
TXD
LBUS
50%
50%
.95VLBUS
.50VBB
.0++++++++++++++++++++++++---5V
0.0V
TTRANSPDR
TTRANSPDF
TRECPDF
TRECPDR
50%
RXD
50%
Internal TXD/RXD
Compare
Match
Match
Match
Match
Match
FAULT Sampling
TFAULT
Stable
TFAULT
Stable
Hold
Value
Hold
Value
FAULT/TXE Output
Stable
FIGURE 2-5:
REGULATOR CS/LWAKE TIMING DIAGRAM
CS/LWAKE
TCSOR
VREG
VOUT
TCSPD
© 2009 Microchip Technology Inc.
DS22018E-page 23