Micrel, Inc.
KS8721BL/SL
Pin Description
Pin Number
1
2
3
Pin Name
MDIO
MDC
RXD3/
PHYAD
Type
(1)
I/O
I
Ipd/O
Pin Function
Management Independent Interface (MII) Data I/O. This pin requires an external 4.7K
pull-up resistor.
MII Clock Input. This pin is synchronous to the MDIO.
MII Receive Data Output. RXD [3..0], these bits are synchronous with RXCLK.
When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.
RXD [3..0] is invalid when RXDV is de-asserted.
During reset, the pull-up/pull-down value is latched as PHYADDR [1]. See “Strapping
Options” section for details.
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR[2]. See “Strapping
Options” section for details.
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR[3]. See “Strapping
Options” section for details.
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR[4]. See “Strapping
Options” section for details.
Digital IO 2.5 /3.3V tolerant power supply. 3.3V power Input of voltage regulator. See
“Circuit Design Ref. for Power Supply" section for details.
Ground.
MII Receive Data Valid Output.
During reset, the pull-up/pull-down value is latched as PCS_LPBK. See “Strapping
Options” section for details.
MII Receive Clock Output. Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
MII Receive Error Output.
During reset, the pull-up/pull-down value is latched as ISOLATE during reset. See
“Strapping Options” section for details.
Ground.
Digital core 2.5V only power supply. See “Circuit Design Ref. for Power Supply" section
for details.
MII Transmit Error Input.
MII Transmit Clock Output.
Input for crystal or an external 50MHz clock. When REFCLK pin is used for REF clock
interface, pull up XI to VDDPLL 2.5V via 10kΩ resistor and leave XO pin unconnected.
MII Transmit Enable Input.
MII Transmit Data Input.
MII Transmit Data Input.
MII Transmit Data Input.
MII Transmit Data Input.
MII Collision Detect Output.
During reset, the pull-up/pull-down value is latched as RMII select. See “Strapping
Options” section for details.
MII Carrier Sense Output.
During reset, the pull-up/pull-down value is latched as RMII back-to-back mode when
RMII mode is selected. See “Strapping Options” section for details.
Ground.
4
RXD2/
PHYAD2
RXD1/
PHYAD3
RXD0/
PHYAD4
VDDIO
GND
RXDV/
CRSDV/
PCS_LPBK
RXC
RXER/ISO
Ipd/O
5
Ipd/O
6
Ipd/O
7
8
9
P
Gnd
Ipd/O
10
11
O
Ipd/O
12
13
14
15
GND
VDDC
TXER
TXC/
REFCLK
TXEN
TXD0
TXD1
TXD2
TXD3
COL/
RMII
CRS/
RMII_BTB
GND
Gnd
P
Ipd
I/O
16
17
18
19
20
21
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd/O
22
Ipd/O
23
Gnd
June 2009
7
M9999-062509-1.3
MICROCHIP [ MICROCHIP TECHNOLOGY ]
