Micrel, Inc.
KS8721BL/SL
Functional Description
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel to serial conversion, NRZ-to-NRZI conversion, and MLT-3
encoding and transmission. The circuitry starts with a parallel to serial conversion that converts the 25MHz, 4-bit
nibbles into a 125MHz serial bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The
serialized data is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The output
current is set by an external 1% 6.49kΩ resistor for the 1:1 transformer ratio. Its typical rise/fall time of 4ns complies
with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-
T output driver is also incorporated into the 100BASE-TX driver.
100BASE-TX Receive
The 100BASE-TX receive function performs adaptive equalization, DC restoration, MLT-3 to NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, and serial-to-parallel conversion. The receiving side starts with the
equalization
filter
to compensate inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss
and phase distortion are a function of the length of the cable, the equalizer has to adjust its characteristic to optimize
performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming
signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process
and can self-adjust for environmental changes such as temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effects of base line wander and improve dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B
nibbles. A synchronized 25MHz RXC is generated so that the 4B nibbles are clocked out at the negative edge of
RCK25 and is valid for the receiver at the positive edge. When no valid data is present, the clock recovery circuit is
locked to the 25MHz reference clock and both TXC and RXC clocks continue to run.
PLL Clock Synthesizer
The KS8721BL/SL generates 125MHz, 25MHz, and 20MHz clocks for system timing. An internal crystal oscillator circuit
provides the reference clock for the synthesizer.
Scrambler/De-scrambler (100BASE-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce electromagnetic
interference (EMI) and baseline wander.
10BASE-T Transmit
When TXEN (transmit enable) goes high, data encoding and transmission begins. The KS8721BL/SL continues to
encode and transmit data as long as TXEN remains high. The data transmission ends when TXEN goes low. The last
transition occurs at the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one.
The output driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics. They are
internally wave-shaped and pre-emphasized into outputs with typical 2.5V amplitude. The harmonic contents are at
least 27dB below the fundamental when driven by all-ones, Manchester-encoded signal.
10BASE-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit
and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and
NRZ data. A squelch circuit rejects signals with levels less than 300mV or with short pulse widths in order to prevent
noise at the RX+ or RX- input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL
locks onto the incoming signal and the KS8721BL/SL decodes a data frame. This activates the carrier sense (CRS) and
RXDV signals and makes the receive data (RXD) available. The receive clock is maintained active during idle periods in
between data reception.
June 2009
11
M9999-062509-1.3
MICROCHIP [ MICROCHIP TECHNOLOGY ]
