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KSZ8041NLITR 参数 Datasheet PDF下载

KSZ8041NLITR图片预览
型号: KSZ8041NLITR
PDF下载: 下载PDF文件 查看货源
内容描述: [DATACOM, ETHERNET TRANSCEIVER, QCC32, 5 X 5 MM, LEAD FREE, MLF-32]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 54 页 / 671 K
品牌: MICROCHIP [ MICROCHIP ]
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Micrel, Inc.  
KSZ8041NL/RNL  
Strapping Options – KSZ8041NL  
Type(1)  
Pin Number Pin Name  
Pin Function  
15  
14  
13  
PHYAD2  
PHYAD1  
PHYAD0  
Ipd/O  
The PHY Address is latched at power-up / reset and is configurable to any value from  
1 to 7.  
Ipd/O  
Ipu/O  
The default PHY Address is 00001.  
PHY Address bits [4:3] are always set to ‘00’.  
18  
29  
28  
CONFIG2  
CONFIG1  
CONFIG0  
Ipd/O  
Ipd/O  
Ipd/O  
The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined as  
follows:  
CONFIG[2:0]  
Mode  
000  
MII (default)  
001  
RMII  
010  
Reserved – not used  
Reserved – not used  
MII 100Mbps Preamble Restore  
Reserved – not used  
Reserved – not used  
Reserved – not used  
011  
100  
101  
110  
111  
20  
31  
ISO  
Ipd/O  
Ipu/O  
ISOLATE mode  
Pull-up = Enable  
Pull-down (default) = Disable  
During power-up / reset, this pin value is latched into register 0h bit 10.  
SPEED mode  
SPEED  
Pull-up (default) = 100Mbps  
Pull-down = 10Mbps  
During power-up / reset, this pin value is latched into register 0h bit 13 as the Speed  
Select, and also is latched into register 4h (Auto-Negotiation Advertisement) as the  
Speed capability support.  
16  
DUPLEX  
NWAYEN  
Ipu/O  
Ipu/O  
DUPLEX mode  
Pull-up (default) = Half Duplex  
Pull-down = Full Duplex  
During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex  
Mode.  
30  
Nway Auto-Negotiation Enable  
Pull-up (default) = Enable Auto-Negotiation  
Pull-down = Disable Auto-Negotiation  
During power-up / reset, this pin value is latched into register 0h bit 12.  
Note:  
1. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.  
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.  
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during  
power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII signals to be latched high. In this  
case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to  
ISOLATE mode, or is not configured with an incorrect PHY Address.  
September 2010  
14  
M9999-090910-1.4