Micrel, Inc.
KSZ8041NL/RNL
Pin Description – KSZ8041RNL
Type(1)
Pin Number Pin Name
Pin Function
1
2
3
4
5
6
7
8
GND
Gnd
P
Ground
VDDPLL_1.8
VDDA_3.3
RX-
1.8V analog VDD
P
3.3V analog VDD
I/O
I/O
I/O
I/O
O
Physical receive or transmit signal (- differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (- differential)
Physical transmit or receive signal (+ differential)
Crystal feedback – for 25 MHz crystal
This pin is a no connect if oscillator or external clock source is used.
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm
RX+
TX-
TX+
XO
9
XI
I
10
REXT
I/O
Set physical transmit output current
Connect a 6.49KΩ resistor in parallel with a 100pF capacitor to ground on this
pin. See KSZ8041RNL reference schematics.
11
12
MDIO
MDC
I/O
I
Management Interface (MII) Data I/O
This pin requires an external 4.7KΩ pull-up resistor.
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
13
14
15
PHYAD0
PHYAD1
Ipu/O
Ipd/O
Ipd/O
The pull-up/pull-down value is latched as PHYADDR[0] during power-up / reset.
See “Strapping Options” section for details.
The pull-up/pull-down value is latched as PHYADDR[1] during power-up / reset.
See “Strapping Options” section for details.
RMII Mode:
RMII Receive Data Output[1](2)
/
RXD1 /
PHYAD2
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
RMII Receive Data Output[0](2)
/
16
RXD0 /
Ipu/O
RMII Mode:
DUPLEX
Config Mode:
Latched as DUPLEX (register 0h, bit 8) during power-up /
reset. See “Strapping Options” section for details.
17
18
VDDIO_3.3
CRS_DV /
CONFIG2
P
3.3V digital VDD
RMII Mode:
Ipd/O
Carrier Sense/Receive Data Valid Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG2 during
power-up / reset. See “Strapping Options” section for details.
19
20
REF_CLK
O
50MHz Clock Output
This pin provides the 50MHz RMII reference clock output to the MAC.
RX_ER /
ISO
Ipd/O
RMII Mode:
RMII Receive Error Output /
Config Mode:
The pull-up/pull-down value is latched as ISOLATE during
power-up / reset. See “Strapping Options” section for details.
21
INTRP
Opu
Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for programming the
interrupt conditions and reading the interrupt status. Register 1Fh bit 9 sets the
interrupt output to active low (default) or active high.
22
23
NC
O
I
No connect
TX_EN
RMII Transmit Enable Input
September 2010
16
M9999-090910-1.4
MICROCHIP [ MICROCHIP ]
