ENC28J60
REGISTER 12-3: EIR: ETHERNET INTERRUPT REQUEST (FLAG) REGISTER
U-0
—
R-0
R/C-0
R-0
R/C-0
TXIF
R-0
r
R/C-0
R/C-0
PKTIF
DMAIF
LINKIF
TXERIF
RXERIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
PKTIF: Receive Packet Pending Interrupt Flag bit
1= Receive buffer contains one or more unprocessed packets; cleared when PKTDEC is set
0= Receive buffer is empty
bit 5
bit 4
bit 3
DMAIF: DMA Interrupt Flag bit
1= DMA copy or checksum calculation has completed
0= No DMA interrupt is pending
LINKIF: Link Change Interrupt Flag bit
1= PHY reports that the link status has changed; read PHIR register to clear
0= Link status has not changed
TXIF: Transmit Interrupt Flag bit
1= Transmit request has ended
0= No transmit interrupt is pending
bit 2
bit 1
Reserved: Maintain as ‘0’
TXERIF: Transmit Error Interrupt Flag bit
1= A transmit error has occurred
0= No transmit error has occurred
bit 0
RXERIF: Receive Error Interrupt Flag bit
1= A packet was aborted because there is insufficient buffer space or the packet count is 255
0= No receive error interrupt is pending
DS39662B-page 66
Preliminary
© 2006 Microchip Technology Inc.
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