ENC28J60
REGISTER 12-4: PHIE: PHY INTERRUPT ENABLE REGISTER
R-0
r
R-0
r
R-0
r
R-0
r
R-0
r
R-0
r
R-0
r
R-0
r
bit 15
bit 8
R-0
r
R-0
r
R/W-0
r
R/W-0
R-0
r
R-0
r
R/W-0
PGEIE
R/W-0
r
PLNKIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5
Reserved: Write as ‘0’, ignore on read
Reserved: Maintain as ‘0’
bit 4
PLNKIE: PHY Link Change Interrupt Enable bit
1= PHY link change interrupt is enabled
0= PHY link change interrupt is disabled
bit 3-2
bit 1
Reserved: Write as ‘0’, ignore on read
PGEIE: PHY Global Interrupt Enable bit
1= PHY interrupts are enabled
0= PHY interrupts are disabled
bit 0
Reserved: Maintain as ‘0’
REGISTER 12-5: PHIR: PHY INTERRUPT REQUEST (FLAG) REGISTER
R-x
r
R-x
r
R-x
r
R-x
r
R-x
r
R-x
r
R-x
r
R-x
r
bit 15
bit 8
bit 0
R-x
r
R-x
r
R-0
r
R/SC-0
PLNKIF
R-0
r
R/SC-0
PGIF
R-x
r
R-0
r
bit 7
Legend:
R = Readable bit
-n = Value at POR
SC = Self-clearing bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5
Reserved: Do not modify
Reserved: Read as ‘0’
bit 4
PLNKIF: PHY Link Change Interrupt Flag bit
1= PHY link status has changed since PHIR was last read; resets to ‘0’ when read
0= PHY link status has not changed since PHIR was last read
bit 3
bit 2
Reserved: Read as ‘0’
PGIF: PHY Global Interrupt Flag bit
1= One or more enabled PHY interrupts have occurred since PHIR was last read; resets to ‘0’ when read
0= No PHY interrupts have occurred
bit 1
bit 0
Reserved: Do not modify
Reserved: Read as ‘0’
© 2006 Microchip Technology Inc.
Preliminary
DS39662B-page 67
MICROCHIP [ MICROCHIP ]
