ENC28J60
TABLE 15-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE SELF-TEST CONTROLLER
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
ECON1
TXRST
RXRST
DMAST CSUMEN TXRTS
RXEN
BSEL1
BSEL0
13
13
13
13
ERXNDL
ERXNDH
RX End Low Byte (ERXND<7:0>)
—
—
—
RX End High Byte (ERXND<12:8>)
EDMASTL DMA Start Low Byte (EDMAST<7:0>)
EDMASTH DMA Start High Byte (EDMAST<12:8>)
EDMANDL DMA End Low Byte (EDMAND<7:0>)
EDMANDH DMA End High Byte (EDMAND<12:8>)
—
—
—
13
13
13
13
13
14
14
14
14
—
—
—
EDMACSL DMA Checksum Low Byte (EDMACS<7:0>)
EDMACSH DMA Checksum High Byte (EDMACS<15:8>)
EBSTSD
Built-in Self-Test Fill Seed (EBSTSD<7:0>)
PSV2 PSV1 PSV0 PSEL
Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>)
EBSTCON
EBSTCSL
TMSEL1 TMSEL0
TME
BISTST
EBSTCSH Built-in Self-Test Checksum High Byte (EBSTCS<15:8>)
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used.
© 2006 Microchip Technology Inc.
Preliminary
DS39662B-page 77
MICROCHIP [ MICROCHIP ]
