ENC28J60
12.1.5
LINK CHANGE INTERRUPT
FLAG (LINKIF)
12.1.6
DMA INTERRUPT FLAG (DMAIF)
The DMA interrupt indicates that the DMA module has
completed its memory copy or checksum calculation
(ECON1.DMAST has transitioned from ‘1’ to ‘0’). Addi-
tionally, this interrupt will be caused if the host controller
cancels a DMA operation by manually clearing the
DMAST bit. Once set, DMAIF can only be cleared by the
host controller or by a Reset condition. If the DMA
interrupt is enabled (EIE.DMAIE = 1and EIE.INTIE = 1),
an interrupt is generated by driving the INT pin low. If the
DMA interrupt is not enabled (EIE.DMAIE = 0 or
EIE.INTIE = 0), the host controller may poll the
ENC28J60 for the DMAIF and take appropriate action.
Once processed, the host controller should use the BFC
command to clear the EIR.DMAIF bit.
The LINKIF indicates that the link status has changed.
The actual current link status can be obtained from the
PHSTAT1.LLSTAT or PHSTAT2.LSTAT (see Register 3-5
and Register 3-6). Unlike other interrupt sources, the link
status change interrupt is created in the integrated PHY
module; additional steps must be taken to enable it.
By Reset default, LINKIF is never set for any reason. To
receive it, the host controller must set the
PHIE.PLNKIE and PGEIE bits. After setting the two
PHY interrupt enable bits, the LINKIF bit will then
shadow the contents of the PHIR.PGIF bit. The PHY
only supports one interrupt, so the PGIF bit will always
be the same as the PHIR.PLNKIF bit (when both PHY
enable bits are set).
12.1.7
RECEIVE PACKET PENDING
INTERRUPT FLAG (PKTIF)
Once LINKIF is set, it can only be cleared by the host
controller or by a Reset. If the link change interrupt
The Receive Packet Pending Interrupt Flag (PKTIF) is
used to indicate the presence of one or more data pack-
ets in the receive buffer and to provide a notification
means for the arrival of new packets. When the receive
buffer has at least one packet in it, EIR.PKTIF will be set.
In other words, this interrupt flag will be set anytime the
Ethernet Packet Count register (EPKTCNT) is non-zero.
If the receive packet pending interrupt is enabled
(EIE.PKTIE = 1and EIE.INTIE = 1), an interrupt will be
generated by driving the INT pin low whenever a new
packet is successfully received and written into the
receive buffer. If the receive packet pending interrupt is
not enabled (EIE.PKTIE = 0or EIE.INTIE = 0), the host
controller will not be notified when new packets arrive.
However, it may poll the PKTIF bit and take appropriate
action.
is enabled (EIE.LINKIE
=
1, EIE.INTIE
=
1,
PHIE.PLNKIE = 1 and PHIE.PGEIE = 1), an interrupt
will be generated by driving the INT pin low. If the link
change interrupt is not enabled (EIE.LINKIE = 0,
EIE.INTIE = 0, PHIE.PLNKIE = 0or PHIE.PGEIE = 0),
the host controller may poll the ENC28J60 for the
PHIR.PLNKIF bit and take appropriate action.
The LINKIF bit is read-only. Because reading from PHY
registers requires non-negligible time, the host controller
may instead set PHIE.PLNKIE and PHIE.PGEIE and
then poll the EIR.LINKIF bit. Performing an MII read on
the PHIR register will clear the LINKIF, PGIF and
PLNKIF bits automatically and allow for future link status
change interrupts. See Section 3.3 “PHY Registers”
for information on accessing the PHY registers.
The PKTIF bit can only be cleared by the host controller
or by a Reset condition. In order to clear PKTIF, the
EPKTCNT register must be decremented to ‘0’. See
Section 7.2 “Receiving Packets” for more informa-
tion about clearing the EPKTCNT register. If the last
data packet in the receive buffer is processed,
EPKTCNT will become zero and the PKTIF bit will
automatically be cleared.
© 2006 Microchip Technology Inc.
Preliminary
DS39662B-page 69
MICROCHIP [ MICROCHIP ]
