ENC28J60
Upon any of these conditions, the EIR.TXERIF flag is set
to ‘1’. Once set, it can only be cleared by the host
controller or by a Reset condition. If the transmit error
interrupt is enabled (EIE.TXERIE = 1and EIE.INTIE = 1),
an interrupt is generated by driving the INT pin low for
one OSC1 period. If the transmit error interrupt is not
enabled (EIE.TXERIE = 0 or EIE.INTIE = 0), the host
controller may poll the ENC28J60 for the TXERIF and
take appropriate action. Once the interrupt is processed,
the host controller should use the BFC command to clear
the EIR.TXERIF bit.
12.1.2
RECEIVE ERROR INTERRUPT
FLAG (RXERIF)
The Receive Error Interrupt Flag (RXERIF) is used to
indicate a receive buffer overflow condition. Alternately,
this interrupt may indicate that too many packets are in
the receive buffer and more cannot be stored without
overflowing the EPKTCNT register.
When a packet is being received and the receive buffer
runs completely out of space, or EPKTCNT is 255 and
cannot be incremented, the packet being received will
be aborted (permanently lost) and the EIR.RXERIF bit
will be set to ‘1’. Once set, RXERIF can only be cleared
by the host controller or by a Reset condition. If the
receive error interrupt and INT interrupt are enabled
(EIE.RXERIE = 1 and EIE.INTIE = 1), an interrupt is
generated by driving the INT pin low. If the receive error
interrupt is not enabled (EIE.RXERIE = 0or EIE.INTIE
= 0), the host controller may poll the ENC28J60 for the
RXERIF and take appropriate action.
After a transmit abort, the TXRTS bit will be cleared, the
ESTAT.TXABRT bit will be set and the transmit status
vector will be written at ETXND + 1. The MAC will not
automatically attempt to retransmit the packet. The
host controller may wish to read the transmit status
vector and LATECOL bit to determine the cause of the
abort. After determining the problem and solution, the
host controller should clear the LATECOL (if set) and
TXABRT bits so that future aborts can be detected
accurately.
Normally, upon the receive error condition, the host
controller would process any packets pending from the
receive buffer and then make additional room for future
packets by advancing the ERXRDPT registers (low
byte first) and decrementing the EPKTCNT register.
See Section 7.2.4 “Freeing Receive Buffer Space”
for more information on processing packets. Once
processed, the host controller should use the BFC
command to clear the EIR.RXERIF bit.
In Full-Duplex mode, condition 5 is the only one that
should cause this interrupt. Collisions and other prob-
lems related to sharing the network are not possible on
full-duplex networks. The conditions which cause the
transmit error interrupt meet the requirements of the
transmit interrupt. As a result, when this interrupt
occurs, TXIF will also be simultaneously set.
12.1.4
TRANSMIT INTERRUPT
FLAG (TXIF)
12.1.3
TRANSMIT ERROR INTERRUPT
FLAG (TXERIF)
The Transmit Interrupt Flag (TXIF) is used to indicate
that the requested packet transmission has ended
(ECON1.TXRTS has transitioned from ‘1’ to ‘0’). Upon
transmission completion, abort or transmission cancella-
tion by the host controller, the EIR.TXIF flag will be set to
‘1’. If the host controller did not clear the TXRTS bit and
the ESTAT.TXABRT bit is not set, then the packet was
successfully transmitted. Once TXIF is set, it can only be
cleared by the host controller or by a Reset condition. If
the transmit interrupt is enabled (EIE.TXIE = 1 and
EIE.INTIE = 1), an interrupt is generated by driving the
INT pin low. If the transmit interrupt is not enabled
(EIE.TXIE = 0or EIE.INTIE = 0), the host controller may
poll the ENC28J60 for the TXIF bit and take appropriate
action. Once processed, the host controller should use
the BFC command to clear the EIR.TXIF bit.
The Transmit Error Interrupt Flag (TXERIF) is used to
indicate that a transmit abort has occurred. An abort
can occur because of any of the following:
1. Excessive collisions occurred as defined by the
Retransmission Maximum (RETMAX) bits in the
MACLCON1 register.
2. A late collision occurred as defined by the
Collision Window (COLWIN) bits in the
MACLCON2 register.
3. A collision after transmitting 64 bytes occurred
(ESTAT.LATECOL set).
4. The transmission was unable to gain an
opportunity to transmit the packet because the
medium was constantly occupied for too long.
The deferral limit (2.4287 ms) was reached and
the MACON4.DEFER bit was clear.
5. An attempt to transmit a packet larger than the
maximum frame length defined by the MAMXFL
registers was made without setting the
MACON3.HFRMEN bit or per packet
POVERRIDE and PHUGEEN bits.
DS39662B-page 68
Preliminary
© 2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
