Figure 8-1. Reset Logic
DATA BUS
MCU Status
Register (MCUSR)
Power-on Reset
Circuit
Brown-out
Reset Circuit
BODLEVEL [2..0]
Pull-up Resistor
SPIKE
FILTER
RSTDISBL
Watchdog
Oscillator
Delay Counters
Clock
CK
Generator
TIMEOUT
CKSEL[3:0]
SUT[1:0]
Table 8-1.
Reset Characteristics
Symbol
Parameter
Min(1)
0.7
Typ(1)
1.0
Max(1)
Units
V
Power-on Reset Threshold Voltage (rising)
Power-on Reset Threshold Voltage (falling)(2)
RESET Pin Threshold Voltage
1.4
1.3
VPOT
0.6
0.9
V
VRST
tRST
0.2 VCC
0.9 VCC
2.5
V
Minimum pulse width on RESET Pin
µs
Notes: 1. Values are guidelines only. Actual values are TBD.
2. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)
8.0.3
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in Table 8-1. The POR is activated whenever VCC is below the detection level. The
POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply
voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay,
when VCC decreases below the detection level.
44
ATmega48/88/168
2545E–AVR–02/05