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ATMEGA88-20AU 参数 Datasheet PDF下载

ATMEGA88-20AU图片预览
型号: ATMEGA88-20AU
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 8KB FLASH 32TQFP]
分类和应用: 时钟ATM异步传输模式PC微控制器外围集成电路闪存
文件页数/大小: 359 页 / 2546 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号ATMEGA88-20AU的Datasheet PDF文件第146页浏览型号ATMEGA88-20AU的Datasheet PDF文件第147页浏览型号ATMEGA88-20AU的Datasheet PDF文件第148页浏览型号ATMEGA88-20AU的Datasheet PDF文件第149页浏览型号ATMEGA88-20AU的Datasheet PDF文件第151页浏览型号ATMEGA88-20AU的Datasheet PDF文件第152页浏览型号ATMEGA88-20AU的Datasheet PDF文件第153页浏览型号ATMEGA88-20AU的Datasheet PDF文件第154页  
Table 15-4 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase cor-  
rect PWM mode.  
Table 15-4. Compare Output Mode, Phase Correct PWM Mode(1)  
COM2A1  
COM2A0  
Description  
0
0
Normal port operation, OC2A disconnected.  
WGM22 = 0: Normal Port Operation, OC2A Disconnected.  
WGM22 = 1: Toggle OC2A on Compare Match.  
0
1
1
1
0
1
Clear OC2A on Compare Match when up-counting. Set OC2A on  
Compare Match when down-counting.  
Set OC2A on Compare Match when up-counting. Clear OC2A on  
Compare Match when down-counting.  
Note:  
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-  
pare Match is ignored, but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on  
page 146 for more details.  
• Bits 5:4 – COM2B1:0: Compare Match Output B Mode  
These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0  
bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected  
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin  
must be set in order to enable the output driver.  
When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the  
WGM22:0 bit setting. Table 15-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits  
are set to a normal or CTC mode (non-PWM).  
Table 15-5. Compare Output Mode, non-PWM Mode  
COM2B1  
COM2B0  
Description  
0
0
1
1
0
1
0
1
Normal port operation, OC2B disconnected.  
Toggle OC2B on Compare Match  
Clear OC2B on Compare Match  
Set OC2B on Compare Match  
Table 15-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM  
mode.  
Table 15-6. Compare Output Mode, Fast PWM Mode(1)  
COM2B1  
COM2B0  
Description  
0
0
1
1
0
1
0
1
Normal port operation, OC2B disconnected.  
Reserved  
Clear OC2B on Compare Match, set OC2B at TOP  
Set OC2B on Compare Match, clear OC2B at TOP  
Note:  
1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-  
pare Match is ignored, but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on  
page 146 for more details.  
150  
ATmega48/88/168  
2545E–AVR–02/05  
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