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ATMEGA88-20AU 参数 Datasheet PDF下载

ATMEGA88-20AU图片预览
型号: ATMEGA88-20AU
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 8KB FLASH 32TQFP]
分类和应用: 时钟ATM异步传输模式PC微控制器外围集成电路闪存
文件页数/大小: 359 页 / 2546 K
品牌: MICROCHIP [ MICROCHIP ]
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generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This fea-  
ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output  
Compare unit is enabled in the fast PWM mode.  
15.6.4  
Phase Correct PWM Mode  
The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct  
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope  
operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-  
TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In non-  
inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match  
between TCNT2 and OCR2x while upcounting, and set on the compare match while downcount-  
ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has  
lower maximum operation frequency than single slope operation. However, due to the symmet-  
ric feature of the dual-slope PWM modes, these modes are preferred for motor control  
applications.  
In phase correct PWM mode the counter is incremented until the counter value matches TOP.  
When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal  
to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown  
on Figure 15-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating  
the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The  
small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x  
and TCNT2.  
Figure 15-7. Phase Correct PWM Mode, Timing Diagram  
OCnx Interrupt Flag Set  
OCRnx Update  
TOVn Interrupt Flag Set  
TCNTn  
(COMnx1:0 = 2)  
OCnx  
(COMnx1:0 = 3)  
OCnx  
1
2
3
Period  
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The  
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM  
value.  
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the  
OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM  
146  
ATmega48/88/168  
2545E–AVR–02/05  
 
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