Figure 11-2. Prescaler for Timer/Counter0 and Timer/Counter1(1)
clkI/O
10-bit T/C Prescaler
Clear
PSRSYNC
T0
T1
Synchronization
Synchronization
0
0
CS10
CS11
CS12
CS00
CS01
CS02
Timer/Counter1 Clock Source
clkT1
Timer/Counter0 Clock Source
clkT0
Note:
1. The synchronization logic on the input pins (Tn) is shown in Figure 11-1.
11.3.1 General Timer/Counter Control Register – GTCCR
Bit
7
6
ICPSEL1
R/W
5
–
4
–
3
–
2
–
1
–
0
TSM
R/W
0
PSRSYNC GTCCR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R/W
0
0
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter synchronization mode. In this mode, the value that is written to the
PSRSYNC bit is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the
corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing
during configuration. When the TSM bit is written to zero, the PSRSYNC bit is cleared by hardware, and the Timer/Counters
start counting simultaneously.
• Bit6 – ICPSEL1: Timer 1 Input Capture Selection
Timer 1 capture function has two possible inputs ICP1A (PD4) and ICP1B (PC3). The selection is made thanks to ICPSEL1
bit as described in Table 11-1.
Table 11-1. ICPSEL1
ICPSEL1
Description
0
1
Select ICP1A as trigger for timer 1 input capture
Select ICP1B as trigger for timer 1 input capture
• Bit 0 – PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by
hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset
of this prescaler will affect both timers.
76
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
