10.2.7 Pin Change Mask Register 1 – PCMSK1
Bit
7
6
5
4
3
2
1
0
PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1
Read/Write
Initial Value
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bit 7 – Res: Reserved Bit
This bit is an unused bit in the ATmega16/32/64/M1/C1, and will always read as zero.
• Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8
Each PCINT15..8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is set and
the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is cleared, pin
change interrupt on the corresponding I/O pin is disabled.
10.2.8 Pin Change Mask Register 0 – PCMSK0
Bit
7
6
5
4
3
2
1
0
PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the
PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change
interrupt on the corresponding I/O pin is disabled.
74
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
