Figure 22-2. Amplifier, Comparator and ADC
Comparator
Clock
ACMPx
+
-
Amplifier
Clock
Analog Comparator
Output
AMPx
Analog Comparator
Negative Input
AMPx+
+
ACxEN
-
AMPx-
AMPCMPx
ADC
Sampling
and Hold
ADC Multiplexer
22.4 Analog Peripheral Clock Sources
22.4.1 ADC Clock
The ADC clock comes from the clock system (CLKio) and it is divided by the ADC Prescaler. See Section 18-6 “ADC
Prescaler Selection” on page 212 The bits described in the ADC Prescaler Selection determine the division factor between
the system clock frequency and input clock of the ADC.
See Section 18.4 “Prescaling and Conversion Timing” on page 200 for a complete description of the ADC clock system.
22.4.2 Comparator Clock
While it is not connected to an amplifier, a comparator is clocked by the comparator clock which is configured thanks to the
ACCKSEL bit in AC0CON register, see Section 20.4.1 “Analog Comparator 0 Control Register – AC0CON” on page 227.
One can select between the 16MHz PLL output and the CLKio.
When it is connected to an amplifier, a comparator is clock by twice the amplifier clock.
22.4.3 Amplifier Clock
When the amplifier uses the ADC clock, this clock is divided by 8. This insures a maximum frequency of 250kHz for the
amplifier when the ADC clock is 2MHz. When the ADC is clocked with a frequency higher than 2MHz the amplifier cannot be
clocked by the ADC clock.
See Section 18.10 “Amplifier” on page 214 for a complete description of the Amplifier clock system.
238
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
