21.4.2.2 DALA = 1
Bit
7
DAC9
DAC1
R/W
R/W
0
6
DAC8
DAC0
R/W
R/W
0
5
DAC7
-
4
DAC6
-
3
DAC5
-
2
DAC4
-
1
DAC3
-
0
DAC2
-
DACH
DACL
Read/Write
Initial Value
R/W
R/W
0
R/W
R/W
0
R/W
R/W
0
R/W
R/W
0
R/W
R/W
0
R/W
R/W
0
0
0
0
0
0
0
0
0
To work with the 10-bit DAC, two registers have to be updated. In order to avoid intermediate value, the DAC input values
which are really converted into analog signal are buffered into unreachable registers. In normal mode, the update of the
shadow register is done when the register DACH is written.
In case DAATE bit is set, the DAC input values will be updated on the trigger event selected through DATS bits.
In order to avoid wrong DAC input values, the update can only be done after having written respectively DACL and DACH
registers. It is possible to work on 8-bit configuration by only writing the DACH value. In this case, update is done each
trigger event.
In case DAATE bit is cleared, the DAC is in an automatic update mode. Writing the DACH register automatically update the
DAC input values with the DACH and DACL register values.
It means that whatever is the configuration of the DAATE bit, changing the DACL register has no effect on the DAC output
until the DACH register has also been updated. So, to work with 10 bits, DACL must be written first before DACH. To work
with 8-bit configuration, writing DACH allows the update of the DAC.
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ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15