When the busy signal is set, some registers are locked, user writing is not allowed:
●
●
●
●
●
“LIN Control Register” - LINCR - except LCMD[2..0], LENA and LSWRES,
“LIN Baud Rate Registers” - LINBRRL and LINBRRH,
“LIN Data Length Register” - LINDLR,
“LIN Identifier Register” - LINIDR,
“LIN Data Register” - LINDAT.
If the busy signal is set, the only available commands are:
●
●
●
LCMD[1..0] = 00 b, the abort command is taken into account at the end of the byte,
LENA = 0 and/or LCMD[2] = 0, the kill command is taken into account immediately,
LSWRES = 1, the reset command is taken into account immediately.
Note that, if another command is entered during busy signal, the new command is not validated and the LOVRERR bit flag of
the LINERR register is set. The on-going transfer is not interrupted.
17.5.5.2 Busy Signal in UART Mode
During the byte transmission, the busy signal is set. This locks some registers from being written:
●
●
“LIN Control Register” - LINCR - except LCMD[2..0], LENA and LSWRES,
“LIN Data Register” - LINDAT.
The busy signal is not generated during a byte reception.
17.5.6 Bit Timing
17.5.6.1 Baud rate Generator
The baud rate is defined to be the transfer rate in bits per second (bps):
●
BAUD: Baud rate (in bps),
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fclki/o: System I/O clock frequency,
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LDIV[11..0]: Contents of LINBRRH & LINBRRL registers - (0-4095), the pre-scaler receives clki/o as input clock.
LBT[5..0]: Least significant bits of - LINBTR register- (0-63) is the number of samplings in a LIN or UART bit (default
value 32).
Equation for calculating baud rate:
BAUD = fclki/o / LBT[5..0] x (LDIV[11..0] + 1)
Equation for setting LINDIV value:
LDIV[11..0] = (fclki/o / LBT[5..0] x BAUD) - 1
Note that in reception a majority vote on three samplings is made.
17.5.6.2 Re-synchronization in LIN Mode
When waiting for Rx Header, LBT[5..0] = 32 in LINBTR register. The re-synchronization begins when the BREAK is
detected. If the BREAK size is not in the range (11 bits min., 28 bits max. — 13 bits nominal), the BREAK is refused. The re-
synchronization is done by adjusting LBT[5..0] value to the SYNCH field of the received header (0x55). Then the
PROTECTED IDENTIFIER is sampled using the new value of LBT[5..0]. The re-synchronization implemented in the
controller tolerates a clock deviation of ±20% and adjusts the baud rate in a ±2% range.
The new LBT[5..0] value will be used up to the end of the response. Then, the LBT[5..0] will be reset to 32 for the next
header.
The LINBTR register can be used to re-calibrate the clock oscillator.
The re-synchronization is not performed if the LIN node is enabled as a master.
ATmega16/32/64/M1/C1 [DATASHEET]
183
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
