17.5.4 Configuration
Depending on the mode (LIN or UART), LCONF[1..0] bits of the LINCR register set the controller in the following
configuration (Table 17-3):
Table 17-3. Configuration Table versus Mode
Mode
LCONF[1..0]
00 b
Configuration
LIN standard configuration (default)
No CRC field detection or transmission
Frame_Time_Out disable
01 b
LIN
10 b
11 b
Listening mode
00 b
8-bit data, no parity and 1 stop-bit
8-bit data, even parity and 1 stop-bit
8-bit data, odd parity and 1 stop-bit
Listening mode, 8-bit data, no parity and 1 stop-bit
01 b
UART
10 b
11 b
The LIN configuration is independent of the programmed LIN protocol.
The listening mode connects the internal Tx LIN and the internal Rx LIN together. In this mode, the TXLIN output pin is
disabled and the RXLIN input pin is always enabled. The same scheme is available in UART mode.
Figure 17-6. Listening Mode
internal
Tx LIN
TXLIN
RXLIN
LISTEN
1
0
internal
Rx LIN
17.5.5 Busy Signal
LBUSY bit flag in LINSIR register is the image of the BUSY signal. It is set and cleared by hardware. It signals that the
controller is busy with LIN or UART communication.
17.5.5.1 Busy Signal in LIN Mode
Figure 17-7. Busy Signal in LIN Mode
FRAME SLOT
HEADER
SYNC
RESPONSE
DATA-n
PROTECTED
IDENTIFIER
LIN Bus
1) LBUSY
2) LBUSY
3) LBUSY
BREAK
DATA-0
CHECKSUM
Field
Field
Field
Field
Field
Field
Node providing the master task
Node providing a slave task
Node providing neither the master task, neither a slave task
LIDOK LCMD = Tx or Rx Response
LCMD = Tx Header
LTXOK or LRXOK
182
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
