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ATMEGA16M1-15MZ 参数 Datasheet PDF下载

ATMEGA16M1-15MZ图片预览
型号: ATMEGA16M1-15MZ
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT 16KB FLASH 32QFN]
分类和应用: 微控制器
文件页数/大小: 318 页 / 7595 K
品牌: MICROCHIP [ MICROCHIP ]
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16.5.4 MOb Page  
Every MOb is mapped into a page to save place. The page number is the MOb number. This page number is set in  
CANPAGE register. The other numbers are reserved for factory tests.  
CANHPMOB register gives the MOb having the highest priority in CANSIT registers. It is formatted to provide a direct entry  
for CANPAGE register. Because CANHPMOB codes CANSIT registers, it will be only updated if the corresponding enable  
bits (ENRX, ENTX, ENERR) are enabled (c.f. Figure 16-14 on page 155).  
16.5.5 CAN Data Buffers  
To preserve register allocation, the CAN data buffer is seen such as a FIFO (with address pointer accessible) into a MOb  
selection.This also allows to reduce the risks of un-controlled accesses.  
There is one FIFO per MOb. This FIFO is accessed into a MOb page thanks to the CAN message register.  
The data index (INDX) is the address pointer to the required data byte. The data byte can be read or write. The data index is  
automatically incremented after every access if the AINC* bit is reset. A roll-over is implemented, after data index=7 it is data  
index=0.  
The first byte of a CAN frame is stored at the data index=0, the second one at the data index=1, ...  
16.6 CAN Timer  
A programmable 16-bit timer is used for message stamping and time trigger communication (TTC).  
Figure 16-11. CAN Timer Block Diagram  
clk  
8
CANTCON  
ENFG  
IO  
clk  
CANTIM  
TTC SYNCTTC  
overrun  
OVRTIM  
CANTIM  
TXOK[i]  
RXOK[i]  
"EOF"  
"SOF"  
CANSTM[i]  
CANTTC  
16.6.1 Prescaler  
An 8-bit prescaler is initialized by CANTCON register. It receives the clkIO frequency divided by 8. It provides clkCANTIM  
frequency to the CAN timer if the CAN controller is enabled.  
TclkCANTIM = TclkIO x 8 x (CANTCON [7:0] + 1)  
16.6.2 16-bit Timer  
This timer starts counting from 0x0000 when the CAN controller is enabled (ENFG bit). When the timer rolls over from  
0xFFFF to 0x0000, an interrupt is generated (OVRTIM).  
16.6.3 Time Triggering  
Two synchronization modes are implemented for TTC (TTC bit):  
synchronization on start of frame (SYNCTTC=0),  
synchronization on end of frame (SYNCTTC=1).  
In TTC mode, a frame is sent once, even if an error occurs.  
152  
ATmega16/32/64/M1/C1 [DATASHEET]  
7647O–AVR–01/15  
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