16.8 Interrupts
16.8.1 Interrupt organization
The different interrupts are:
●
●
●
●
●
●
Interrupt on receive completed OK,
Interrupt on transmit completed OK,
Interrupt on error (bit error, stuff error, CRC error, form error, acknowledge error),
Interrupt on frame buffer full,
Interrupt on “Bus Off” setting,
Interrupt on overrun of CAN timer.
The general interrupt enable is provided by ENIT bit and the specific interrupt enable for CAN timer overrun is provided by
ENORVT bit.
Figure 16-14. CAN Controller Interrupt Structure
CANGIE.4 CANGIE.5 CANGIE.3
ENTX
ENRX
ENERR
CANSIT 1/2
SIT[i]
CANSTMOB.6 TXOK[i]
CANSTMOB.5 RXOK[i]
CANSTMOB.4 BERR[i]
CANSTMOB.3 SERR[i]
CANSTMOB.2 CERR[i]
CANSTMOB.1 FERR[i]
CANSTMOB.0 AERR[i]
CANIE 1/2
IEMOB[i]
0
CANGIT.7
CANIT
i
CANGIE.7
ENIT
CANGIE.2 CANGIE.1 CANGIE.6
ENBX ENERG ENBOFF
CANGIT.4
BXOK
CAN IT
CANGIT.3
CANGIT.2
CANGIT.1
CANGIT.0
SERG
CERG
FERG
AERG
CANGIE.0
ENOVRT
CANGIT.6
BOFFI
CANGIT.5 OVRTIM
OVR IT
ATmega16/32/64/M1/C1 [DATASHEET]
155
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
