Figure 3-2
shows the structure of the 32 general purpose working registers in the CPU.
7
R0
R1
R2
…
R13
General
Purpose
Working
Registers
R14
R15
R16
R17
…
R26
R27
R28
R29
R30
R31
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
X-register Low Byte
X-register High Byte
Y-register Low Byte
Y-register High Byte
Z-register Low Byte
Z-register High Byte
0x0D
0x0E
0x0F
0x10
0x11
0
Addr.
0x00
0x01
0x02
Most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle
instructions.
As shown in
Figure 3-2,
each register is also assigned a data memory address, mapping them directly into the first 32
locations of the user data space. Although not being physically implemented as SRAM locations, this memory organization
provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the
file.
3.5.1
The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address
pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described
in
Figure 3-3.
15
X-register
7
R27 (0x1B)
15
Y-register
7
R29 (0x1D)
15
Z-register
7
R31 (0x1F)
ZH
0
ZL
7
R30 (0x1E)
YH
0
YL
7
R28 (0x1C)
0
0
XH
0
XL
7
R26 (0x1A)
0
0
0
0
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and
automatic decrement (see the instruction set reference for details).
14
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
MICROCHIP [ MICROCHIP TECHNOLOGY ]
