3.
AVR CPU Core
3.1
Introduction
This section discusses the AVR® core architecture in general. The main function of the CPU core is to ensure correct
program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and
handle interrupts.
3.2
Architectural Overview
Figure 3-1. Block Diagram of the AVR Architecture
Data Bus 8-bit
Program
Counter
Status and
Control
Flash
Program
Memory
Interrupt
Unit
32 x 8
General
Purpose
Registers
Instruction
Register
SPI
Unit
Instruction
Decoder
Watchdog
Timer
ALU
Analog
Comparator
Control Lines
I/O Module 1
I/O Module 2
I/O Module n
Data
SRAM
EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and
buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions
to be executed in every clock cycle. The program memory is in-system reprogrammable Flash memory.
The fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This
allows single-cycle arithmetic logic unit (ALU) operation. In a typical ALU operation, two operands are output from the
register file, the operation is executed, and the result is stored back in the register file – in one clock cycle.
ATmega16/32/64/M1/C1 [DATASHEET]
11
7647O–AVR–01/15
MICROCHIP [ MICROCHIP ]
