AT24C32D
Read Operations
Figure 8-2.ꢀRandom Read
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7
8
0
9
1
2
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5
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8
9
1
2
3
4
5
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7
8
9
SCL
Device Address Byte
A2 A1
First Word Address Byte
Second Word Address Byte
1
0
1
0
A0
0
X
X
X
X
A11 A10 A9 A8
0
A7 A6 A5 A4 A3 A2 A1 A0
MSB
0
SDA
MSB
MSB
Start Condition
by Master
ACK
from Slave
ACK
from Slave
ACK
from Slave
Dummy Write
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9
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9
1
Data Word (n)
Device Address Byte
A2 A1
0
1
0
A0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
Start Condition
by Master
Stop Condition
by Master
ACK
from Slave
NACK
from Master
8.3
Sequential Read
Sequential reads are initiated by either a current address read or a random read. After the bus master
receives a data word, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it will
continue to increment the word address and serially clock out sequential data words. When the maximum
memory address is reached, the data word address will roll-over and the sequential read will continue
from the beginning of the memory array. All types of read operations will be terminated if the bus master
does not respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the
master may send a Stop condition to complete the protocol, or it can send a Start condition to begin the
next sequence.
Figure 8-3.ꢀSequential Read
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9
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9
SCL
Device Address Byte
A2 A1
Data Word (n)
1
0
1
0
A0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
0
SDA
MSB
Start Condition
by Master
ACK
from Slave
ACK
from Master
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2
3
4
5
6
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9
1
2
3
4
5
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7
8
9
1
2
3
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5
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7
8
9
1
Data Word (n+1)
Data Word (n+2)
Data Word (n+x)
D7 D6 D5 D4 D3 D2 D1 D0
MSB
0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Stop Condition
ACK
from Master
ACK
from Master
NACK by Master
from Master
DS20006047A-page 22
Datasheet
© 2018 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
